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| EL1881C EL1881C Sync Separator, Low Power Features * NTSC, PAL, SECAM, nonstandard video sync separation * Fixed 70 mV slicing of video input levels from 0.5 VP-P to|2 VP-P * Low supply current - 1.5 mA typ. * Single +5V supply * Composite, vertical sync output * Odd/Even field output * Burst/Back porch output * Available in 8-pin DIP and SO package General Description The EL1881C video sync separator is manufactured using Elantec's high performance analog CMOS process. This device extracts sync timing information from both standard and non-standard video input. It provides composite sync, vertical sync, burst/back porch timing and odd/even field detection. Fixed 70mV sync tip slicing provides sync edge detection when the video input level is between 0.5 Vp-p and 2 Vp-p (sync tip amplitude 143 mV to 572 mV). A single external resistor sets all internal timing to adjust for various video standards. The composite sync output follows video in sync pulses, and a vertical sync pulse is output on the rising edge of the first vertical serration following the vertical pre-equalizing string. For non-standard vertical inputs, a default vertical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. The odd/even output indicates field polarity detected during the vertical blanking interval. The EL1881C is plug-in compatible with the industry standard LM1881 and can be substituted for that part in 5V applications with lower required supply current. Applications * * * * * * * * * Video Amplifier PCMCIA Applications A/D Driver Line Driver Portable Computers High Speed Communications RGB Applications Broadcast Equipment Active Filtering Ordering Information Part No. EL1881CN EL1881CS Temp. Range -40C to +85C -40C to +85C Package 8-pin DIP 8-lead SO Outline # MDP0031 MDP0027 Demo Board A dedicated demo board is not available. However, this device can be placed on the EL4584/5 demo board. Connection Diagram EL1881 SO, P-DIP June 26, 1998 Rev A (c) 1995 Elantec, Inc. EL1881C EL1881C Sync Separator, Low Power Absolute Maximum Ratings (T VCC Supply Storage Temperature Lead Temperature (5 sec) Pin Voltages A = 25 C) 7V -65C to +150C 260C -0.5V to VCC+0.5V Operating Ambient Temperature Range Operating Junction Temperature Power Dissipation -40C to +85C 125C 400 mW Important Note: All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefor TJ = TC = TA. Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002. 100% production tested at TA = 25C and QA sample tested at TA = 25C, TMAX and TMIN per QA test plan QCX0002. QA sample tested per QA test plan QCX0002. Parameter is guaranteed (but not tested) by Design and Characterization Data. Parameter is typical value at TA = 25C for information purposes only. DC Characteristics VDD = 5V, TA = 25C, RSET = 681 k3/4, unless otherwise specified. Parameter IDD, Quiescent Clamp Voltage Clamp Discharge Current Clamp Charge Current RSET Pin Reference Voltage VOL Output Low Voltage VOH Output High Voltage VDD = 5V Pin 2, Unloaded Pin 2 = 2V Pin 2 = 1V Pin 6 IOL = 1.6 mA IOH = -40 A IOH = -1.6 mA 4 2.4 Description Min 0.75 1.35 3.2 -2.0 1.20 Typ 1.5 1.5 12 -1.5 1.31 0.4 4.8 3.5 Max 3.0 1.65 16 -0.8 1.44 0.8 Test Level I I I I I I IV I Units mA V A mA V V V Dynamic Characteristics Parameter Comp Sync Prop Delay, tCS Vertical Sync Width, tVS Vertical Sync Default Delay, tVSD Burst/Back Porch Delay, tBD Burst/Back Porch Width, tB Input Dynamic Range Slice Level See Figure 2 Normal or Default trigger, 50%--50% See Figure 3 See Figure 2 See Figure 2 Video input amplitude to maintain 50% slice spec VSLICE/VCLAMP Description Min 20 190 35 250 2.5 0.5 55 70 Typ 45 270 65 450 3.6 Max 90 350 85 650 4.5 2 85 Test Level I I I I I I I Units ns s s ns s VP-P mV 2 EL1881C EL1881C Sync Separator, Low Power Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 Pin Name Composite Sync Out Composite Video In Vertical Sync Out Gnd Burst/Back Porch Output RSET [1] Odd/Even Output VDD 5V Function Composite sync pulse output. Sync pulses start on a falling edge and end on a rising edge. AC coupled composite video input. Sync tip must be at the lowest potential (Positive picture phase). Vertical sync pulse output. The falling edge of Vert Sync is the start of the vertical period. Supply ground. Burst/Back porch output. Low during burst portion of composite video. An external resistor to ground sets all internal timing. A 681k 1% resistor will provide correct timing for NTSC signals. Odd/Even field output. High during odd fields, low during even fields. Transitions occur at start of Vert Sync pulse. Positive supply. (5V) 1. RSET must be a 1% resistor. 3 EL1881C EL1881C Sync Separator, Low Power Typical Performance Curves Supply Current, Quiescent RSET = 681k IDD vs VDD RSET = 681k VCLAMP Voltage RSET = 681k Clamp Discharge Current RSET = 681k VRSET RSET = 681k Clamp Charge Current RSET = 681k 4 EL1881C EL1881C Sync Separator, Low Power RSET vs Horizontal Frequency Burst/Back Porch Width vs RSET VDD = 5V, T = 25C Burst/Back Porch Delay vs RSET VDD = 5V, T = 25C Vertical Sync Width vs RSET VDD = 5V, T = 25C Vertical Default Delay vs RSET VDD = 5V, T = 25C 5 EL1881C EL1881C Sync Separator, Low Power Composite Sync Prop Delay RSET = 681k, VDD = 5V Burst/Back Porch Width, RSET = 681k Burst/Back Porch Delay Time, RSET = 681k Vertical Sync Pulse Width RSET = 681k Vertical Sync Default Delay Time, RSET = 681k Composite Sync to Vertical Sync Delay Time RSET = 681k Composite Sync to Odd/Even Delay Time RSET = 681k 6 EL1881C EL1881C Sync Separator, Low Power Timing Diagrams Notes: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). * Signal 1a drawing reproduced with permission from EIA. Figure 1. Standard (NTSC Input) Timing 7 EL1881C EL1881C Sync Separator, Low Power Expanded Timing Diagrams Figure 2. Standard Vertical Timing Figure 3. Non-Standard Vertical Timing 8 EL1881C EL1881C Sync Separator, Low Power Figure 4. Standard (NTSC Input) H. Sync Detail 9 EL1881C EL1881C Sync Separator, Low Power Applications Information Video In A simplified block diagram is shown following page. An AC coupled video signal is input to Video In pin 2 via C1, nominally 0.1 F. Clamp charge current will prevent the signal on pin 2 from going any more negative than Sync Tip Ref, about 1.5V. This charge current is nominally about 1mA. A clamp discharge current of about 10A is always attempting to discharge C1 to Sync Tip Ref, thus charge is lost between sync pulses that must be replaced during sync pulses. The droop voltage that will occur can be calculated from IT = CV, where V is the droop voltage, I is the discharge current, T is the time between sync pulses (sync period - sync tip width), and C is C1. An NTSC video signal has a horizontal frequency of 15.73 kHz, and a sync tip width of 4.7 s. This gives a period of 63.6 s and a time T = 58.9 s. The droop voltage will then be V = 5.9 mV. This is less than 2% of a nominal sync tip amplitude of 286 mV. The charge represented by this droop is replaced in a time given by T=CV/I, where I = clamp charge current = 1 mA. Here T = 590ns, about 12% of the sync pulse width of 4.7s. It is important to choose C1 large enough so that the droop voltage does not approach the switching threshold of the internal comparator. The vertical cycle starts with a pre-equalizing phase of pulses with a duty cycle of about 93%, followed by a vertical serration phase that has a duty cycle of about 15%. Vertical Sync is clocked out of the EL1881C on the first rising edge during the vertical serration phase. In the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 60 s after the last falling edge of the vertical equalizing phase for RSET = 681 k3/4. Odd/Even Because a typical television picture is composed of two interlaced fields, there is an odd field that includes all the odd lines, and an even field that consists of the even lines. This odd/even field information is decoded by the EL1881C during the end of picture information and the beginning of vertical information. The odd/even circuit includes a T-flip-flop that is reset during full horizontal lines, but not during half lines or vertical equalization pulses. The T-flip-flop is clocked during each falling edge of these half hperiod pulses. Even fields will toggle until a low state is clocked to the odd/even pin 7 at the beginning of vertical sync, and odd fields will cause a high state to be clocked to the odd/even pin at the start of the next vertical sync pulse. Odd/even can be ignored if using non-interlaced video, as there is no change in timing from one field to the next. Fixed Gain Buffer The clamped video signal then passes to the fixed gain buffer which places the sync slice level at the equivalent level of 70 mV above sync tip. The output of this buffer is presented to the comparator, along with the slice reference. The comparator output is level shifted and buffered to TTL levels, and sent out as Composite Sync to pin 1. RSET An external RSET resistor, connected from RSET pin 6 to ground, produces a reference current that is used internally as the timing reference for vertical sync width, vertical sync default delay, burst gate delay and burst width. Decreasing the value of RSET increases the reference current, which in turn decreases reference times and pulse widths. A higher frequency video input necessitates a lower RSET value. Burst A low-going Burst pulse follows each rising edge of sync, and lasts approximately 3.5 s for an RSET of 681 k3/4. Chroma Filter A chroma filter is suggested to increase the S/N ratio of the incoming video signal. Use of the optional chroma filter is shown in Figure 5. It can be implemented very simply and inexpensively with a series resistor of 6203/4 and a parallel capacitor of 500 pF, which gives a single 10 Vertical Sync A low-going Vertical Sync pulse is output during the start of the vertical cycle of the incoming video signal. EL1881C EL1881C Sync Separator, Low Power pole roll-off frequency of about 500kHz. This sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet passes the approximately 15kHz sync signals without appreciable attenuation. A chroma filter will increase the propagation delay from the composite input to the outputs. Figure 5. Simplified Block Diagram * Note: RSET must be a 1% resistor. Figure 6. 11 EL1881C EL1881C Sync Separator, Low Power General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. WARNING - Life Support Policy June 26, 1998 Rev A Elantec, Inc. 1996 Tarob Court Milpitas, CA 95035 Telephone: (408) 945-1323 (800) 333-6314 Fax: (408) 945-9305 European Office: 44-71-482-4596 12 Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.'s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. Printed in U.S.A. |
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